The present invention relates to a substrate bias generating circuit for applying a predetermined bias to a semiconductor substrate.
Integrated circuits, e.g., one chip central processing unit (CPU) or a random access memory (RAM), etc. employing p-type semiconductor substrate and internally containing a substrate bias generating circuit, have recently found increasing use. When such a substrate bias generating circuit is associated with an integrated circuit in this manner, for example, the capacitance of a junction capacitor formed between the substrate and a diffused region formed in the surface region of the substrate can be reduced, a substrate injection current from localized forward biasing of diodes can be eliminated, and the variation of the threshold voltage of an MOS transistor formed in the substrate due to its source body effect can be minimized.
FIG. 1 shows a conventional substrate bias generating circuit. This substrate bias generating circuit has a ring oscillator 2, a capacitor 4 connected at one end to the output terminal of the ring oscillator 2 through a buffer circuit 6, an n-channel MOS transistor 8 connected at its drain and gate to the other end of the capacitor 4 and also connected at its source to a ground terminal VS, and an n-channel MOS transistor 10 connected at its source to the output end of the capacitor 4 and also connected at its drain and gate to a substrate bias terminal VB.
When the potential of the other end of the capacitor 4 is positive in this substrate bias generating circuit, a current will flow through the MOS transistor 8, thereby varying the potential at the other end of the capacitor 4 toward a ground or reference potential. At this time negative charge is stored in the capacitor 4. When the output signal from the buffer circuit 6 becomes a low level, the potential at the other end of the capacitor 4 becomes negative. When the substrate potential of this case is higher than the potential at the other end of the capacitor 4 in the level of the threshold voltage (&gt;0) of the MOS transistor 10, the negative charge stored in the capacitor 4 is flowed into the substrate, thereby lowering the substrate potential.
In the substrate bias generating circuit in FIG. 1, the substrate bias potential VBB varies proportionally to the power voltage VCC applied to a power voltage terminal VC connected to both the oscillator 2 and the buffer circuit 6. In a case where a load is capacitive, when the power source voltage VCC changes, the substrate bias voltage VBB will resultantly vary, and might disadvantageously cause difficulties, e.g., variations in the threshold voltage of an MOS transistor formed in the substrate, an increase in current consumption, etc. It is thus required, for example, in a RAM in a standby mode that consumption current should be minimized and stored data should be maintained with a lower power voltage. When the power voltage is, however, lowered in the RAM in which a conventional substrate bias generating circuit is internally contained, the absolute value of the substrate bias voltage becomes low, with the result, for example, that the threshold voltage (&gt;0) of a depletion type (D-type) MOS transistor formed in the p-type substrate will increase in the negative direction. Consequently, larger leakage current will flow through the D-type MOS transistor, resulting in an increase in its consumption power.